![]() ![]() The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The latch is reset with each clock pulse. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the pe- riod. Another feature of these PWM cir- cuits is a latch following the comparator. This lockout circuitry in- cludes approximately 500 mV of hysteresis for jitter- free operation. These functions are also control- led by an undervoltage lockout which keeps the out- puts off and the soft-start capacitor discharged for sub-normal input voltages. A shutdown terminal controls both the soft-start circu- ity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shut- down, as well as soft-start recycle with longer shut- down commands. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. ![]() A single resistor between the CT and the discharge terminals provide a wide range of dead time ad- justment. A sync input to the oscillator al- lows multiple units to be slaved or a single unit to be synchronized to an external system clock. The on-chip + 5.1 V reference is trimmed to ± 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. The SG3525A series of pulse width modulator inte- grated circuits are designed to offer improved per- formance and lowered external parts count when used in designing all types of switching power sup- plies. INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS ![]()
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